USB 2.0 See also our USB 3.0 products and their data sheets:

Universal Serial Bus 2.0 (High Speed)

This device controller is based on the Vreelin Engineering core which has been used extensively in commercial settings for 5 years. It has the following features:

USB device core
  • Device processor interface
    • Xilinx Local Memory Bus (LMB)
    • ARM Advanced eXtensible Interface (AXI)
  • Dual-port, dual clock ram
    • Can be configured up to 16kx32
  • Serial Interface Engine
    • Uses a ULPI interface to the PHY
    • Any PHY which implements the ULPI interface will work
      • Many have been successful with the SMSC PHY
USB device firmware
  • Code to implement a USB mass storage device
  • Code to implement a wraparound test device
System Model
  • Test bench
  • Processor bus functional model
  • PHY bus functional model
Adapt-IP's USB 2 device core can be ordered in the following configurations:
  • SystemC model for inclusion in a virtual platform system model
  • Synthesizable Verilog RTL for implementation in an FPGA or ASIC
    • For ASIC, specify the required technology (.lib file)
  • Xilinx test board with FPGA and SMSC PHY and 256MB DDR3 memory, with core loaded into the board's flash memory
  • Customized core
    • Adapt IP can customize the core to meet nearly any customer requirements

 


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